The ET-SoC-1's DVFS loop, and the leakage it never switches off

21–24 September 2026, checked on three cards on 25–26 September, and on aifoundry2 a development night on 27–28 September and its frozen validation on 28–29 September (§8) · aifoundry2 and aifoundry3, and in the check aifoundry1's card 1 · the governor the cards run read at et-platform ffca4cbb4 (service-processor bootloader 0.20.0, the closest public source to aifoundry2 and aifoundry3) and da192816a (0.18.0, aifoundry1's card 1); the rewritten governor of 353f20e for comparison (§9) · open RTL core-et b38a1a3 (Erbium branch) · checks five claims from a conversation with David Kanter (MLCommons) on 20 September 2026, in private notes · part of the ET-SoC-1 measurement reports

The ET-SoC-1 manages its power more simply than a mature chip, and leakage is where it pays. Its governor reads a power meter instead of estimating power, and its 65 °C threshold has no dead band, so near it aifoundry2's clock hunts. The temperature it compares is one number, the whole-degree mean of 34 shire sensors, never the hottest one. On aifoundry2 (§8) the clock stepped down with that mean, seconds after the hottest shire had passed the threshold, and the same work placed on the perimeter held 800 MHz longer than placed in the interior, on a development night and again in a frozen validation (28–29 September); but the card idled too warm for the validation to gather the runs its registered tests need, so by its rules both questions stay untested. Its open RTL has per-minion sleep controls that are tied off, and none of three cards shows any sign of array power gating. What is left is leakage. On aifoundry2, idle power climbs W for every degree at 80 °C, and the leakage behind that slope is W, of an idle card by the law's own readings, well above the 5–30% David Kanter called typical; the same readings put it at of a card running a random-data matmul, but whether that exceeds 30% the three-card check could not settle. And on aifoundry3 a boot service sets the firmware's power limit to 0 W (the other cards' is 65 W), which pins it at 600 MHz while the driver still reports 65 W.

Checked on three cards (26 September 2026). This page's claims were re-measured under a pre-registered plan on aifoundry2, aifoundry3 and aifoundry1's card 1 (firmware 1.2.0; the other two run 1.3.1). Of 28 claims tested here: 9 held, 5 corrected, 12 differ by card and 2 not confirmed, as the hub’s scoreboard counts them. No card shows a cache wake-up; the governor settings read as stated, but the log lines that showed aifoundry3's throttling on 22 September did not appear again; the idle law predicts aifoundry2's idle to a tenth of a watt, while aifoundry3's offset from it grows with temperature and aifoundry1's card 1 sits 8–13 W above it; and leakage above 30% of a busy card is not established. The 21–24 September numbers stay, labelled as theirs (the record).
Kanter's yardstick for a mature chip's DVFS loop

The yardstick is how Kanter described a mature chip managing its own power. It runs a DVFS loop (dynamic voltage and frequency scaling) that knows and, because voltage and frequency are already known, computes its own power estimate from activity counters. It folds thermal sensors into the same loop, because leakage depends on temperature. And it puts cache data arrays behind leakage-suppression transistors, so that only the ~10% of an array in use is awake. He hedged that this might not hold for Esperanto's part, only for anything from a more mature company. The hedge was right. The table below checks five of his statements, paraphrased, against the firmware source, the open RTL and the card.

Terms used on this page

DVFS (dynamic voltage and frequency scaling) moves the clock and the supply voltage together: here the service processor (SP), the on-die management core, steps among three operating points, 600, 700 and 800 MHz, each one row of the firmware's frequency-to-voltage table (the VMIN-LUT). It reads board power from the PMIC, the board's power-management controller, and die temperature from the on-die PVT sensors (the integer mean of the 34 minion-shire sensors, each read in whole degrees), and compares them with 65 °C and with TDP, the firmware's power limit of 65 W. The compute cores are minions, 32 to a shire, and kernels run on 32 shires (1,024 minions); the master minion dispatches them and tells the loop whether the card is busy. The flip-counting model is the Horace experiment's model of power from the bits the multiply-add unit clocks and toggles; more in the hub's glossary.

1. The loop as built

aifoundry2 and aifoundry3 run service-processor bootloader 0.20.0 (firmware release 1.3.1), of about mid-May 2024; the closest public source is et-platform ffca4cbb4 (cafe03fc3^). aifoundry1's card 1 runs 0.18.0 (release 1.2.0; da192816a). Earlier versions of this page described the governor as rewritten in September 2024 (353f20e), which the cards do not run; §9 lists how the two differ. Line numbers below are in ServiceProcessorBL2/services/thermal_pwr_mgmt.c at ffca4cbb4 unless another file is named.

The governor the cards run, as pseudocode, and where it lives in the source
every device-management pass: ,
 while a 10 Hz telemetry sampler queries the card, in the SP's own trace
(the board value changes every  in the sampler's stream, §7: the two methods differ by  ms):
    T = pvt_get_minion_avg_temperature()     // integer mean of the 34 minion-shire sensors, each truncated to whole degrees
    P = pmic_read_instantaneous_soc_power()  // MEASURED board power, from the PMIC over I2C
    if T > 65 °C and state < THERMAL_DOWN:                // no test of whether a kernel runs
        state = THERMAL_DOWN, and the power task runs the thermal loop (below)
    elif state < THERMAL_DOWN:                            // the power branch: locked out while the loop runs
        if master minion IDLE:  clock back to the boot point (600 MHz)
        elif P > 65 W:          step DOWN, no delay, until the PMIC average < 1.05 × 65 W or 300 MHz
        elif P < 65 W:          step UP,   no delay, until the PMIC average > 65 W or the top point

thermal loop (the power task; nothing else changes the clock meanwhile):
    repeat: step DOWN one VMIN-LUT point; sleep 1000 ticks ( s of SP time); T = the mean again
    until T <= 65
    then clock back to the boot point, and on the next pass the power branch climbs to the top point in one call

Where each line lives (all "if active power management is on"): the trigger at 668–679, with the threshold TEMP_THRESHOLD_SW_MANAGED 65 at include/thermal_pwr_mgmt.h:46; the mean at driver/pvt_controller.c:1279–1306 (shires 0–33; the I/O shire's sensor is not in it), each reading converted in integer arithmetic, so truncated to a whole degree, at :572–590; the power branch's gate at 844–845, its idle, down and up cases at 848–860, 862–873 and 876–887, reading the instantaneous power at 798–807; the power loops at 2173–2256 (the climb at 2229–2236, the down loop's exit at 2238–2246); the thermal loop at 2316–2361 with its vTaskDelay(pdMS_TO_TICKS(1000)) at 2354, its exit at 2366–2374 and the return to the boot point at 2446–2449 and 1975–1979. The tick is read from the card: the service processor's heartbeat, vTaskDelay(100000), appears in its trace every s of its own clock ( intervals on 27–28 September, §8), so 1000 ticks are s.

Five things follow, and all five show up in aifoundry2's measurements below (aifoundry3's clock cannot move, §3).

The five behaviours, explained

2. The loop as measured

Only aifoundry2's clock has been seen to move (aifoundry3 is held at 600 MHz, §3, and aifoundry1's card 1 read 600 MHz in every sample of the three-card check, even busy and cool enough to climb, §3), so this section is aifoundry2's alone. The rule raises the clock only while the die reads 65 °C or less, which on 21 September meant the first runs after a night of idling. Our 10 Hz samples caught up-steps at readings of °C that morning; . Seven such runs, from the cool-start session on the morning of 21 September (Horace experiment §6), were sampled at 10 Hz and are charted below. They contain clock transitions. Voltage moved with frequency in every one of them: . This is real DVFS, not frequency scaling alone.

Watch the governor decide: the seven cool-start runs on aifoundry2, 21 September, one 10 Hz sample at a time

Pick a run, then play it or drag through it. On the time slider, the arrow keys move one 100 ms sample and Page Up / Page Down jump between clock changes. The panel applies the §1 rule to the sampled die temperature, board power and clock; at a clock change it reads the last sample before the step, and shows the sample after it with a dashed mark.

It hunts, and the missing hysteresis explains it. On aifoundry2 the clock hunted on both days it started cool (). One run shows how: run 3 of 21 September (all ones, from a 64 °C die; the chart opens on it) never brought the board near 65 W (it peaked at 56 W); what the loop kept crossing was the 65 °C line. At a mean of 66 °C the thermal loop starts and steps the clock down one point every s; once the mean re-reads 65 °C at a loop check, the loop sends the clock to the boot point, 600 MHz, and on the next pass the power branch, seeing 38 W < 65 W with a kernel running, climbs straight back to 800 MHz (§1). The clock changed seven times in 2.4 s, reaching 800 MHz twice, 1.6 s apart. Then, with the die settled at 66 °C, it stayed at 600 MHz for the last 4.5 s. Over the whole 7.4 s run it spent 5.6 s at the bottom point, 1.0 s at 700 MHz and 0.8 s at 800 MHz.

How the down-steps split by branch: the plane, the breakdown and the full table
The rule's plane: die temperature against board power, shaded by the branch that fires, with all down-steps and every up-step placed on it

Points within one whole degree are spread sideways so each is visible. Select a point (click, tap or Enter) to replay its step in the chart above.

No down-step is the power branch acting alone. Of the 18, seven were thermal only (the die above 65 °C while the board drew 45–56 W, well under the limit) and four read above both thresholds on the sample after the step (random data draws up to 88 W at 800 MHz and 69 W at 700, and heats fast). The other seven cannot be attributed from our telemetry: the die read 65 °C (once 64) and the board 34–56 W, so neither test fired on the values we sampled. One of them, a single event (run 1, zeros, at 5.95 s: 800→600 MHz in one step, 171 ms after a launch boundary), looks like the boot-point reset, or a thermal loop that found the mean at 65 °C on its first re-read and exited straight to the boot point. (Launches run back to back every 0.37–0.49 s, so nearness to a boundary alone explains nothing.) The other six are single-point steps in pairs 0.4–0.5 s apart, which is the thermal loop's period (§1): the first of each pair a thermal step, taken on a pass where the service processor read a mean of 66 °C between our 10 Hz samples, and a 700→600 MHz step at a reading of 65 °C the loop's exit to the boot point (§9 gives the split read on the sample before each step). The power branch never fired on its own, because on a cool die only random data at 700–800 MHz exceeds 65 W (at 600 MHz it does too, but only on a die above about 82 °C, where the thermal loop already holds the floor), and random data takes the die through 65 °C within half a second. Two drops at high power need a closer look. Run 2 went 800→600 MHz in one step between two samples at 87.5 W; that fits either the power loop or a thermal episode of zero steps, whose loop finds the mean back at 65 °C on its first read and exits straight to the boot point (the same path as run 1's step above, and the commonest episode on the idle card, §8). Run 7 went 800→700→600 MHz within 0.1 s at 87.8 W, and that one cannot be the thermal loop, which steps once per s: in the cards' source only the power loop steps with no delay, so run 7's two steps are most likely the power branch lowering the clock, on passes where the service processor's mean still read 65 (§3; an inference from the source, since our samples there read above both thresholds).

All down-steps as a table

Die °C and board W are the first sample that shows the new clock. The board meter lags the clock by , so a 700→600 MHz step can still show an 800 MHz burst. "Unattributed" means neither test fired on the values we sampled (the die read 65 °C or less and the board under 65 W).

How fast the loop starts, and steps thereafter

The loop is also slow to start: the first clock change came a median s after a block of launches began ( s over starts on 21 and 23 September; s in the seven runs charted), about passes of the loop as it runs under our 10 Hz sampling (about ms per pass, §1). Once moving, it changed the clock a median s after the previous change ( s for the middle 80%), close to the thermal loop's own period, s (§1), rather than a count of passes. up-steps charted () go straight from 600 to 800 MHz between two 100 ms samples, faster than one table point per pass: the cards' governor climbs to the top point in one call (§1), where the September 2024 rewrite would step one point per pass (§9).

3. The governor's settings on three cards

So far the loop has been measured on one card. AI Foundry has three machines, and the loop's behaviour turned out to depend on a single setting that differs between them.

aifoundry1: why it could not be measured on 22 September, and how its card 1 joined the check

aifoundry1 could not be measured on 22 September. It holds two ET-SoC-1 cards, and the management library refused both (Error unable to evaluate compatibility!). The cause, found on 25 September, was an empty version string in the kernel module built there, not the srcversion mismatch this page first blamed; a rebuild of the driver fixed it that day. Its card 1 (firmware 1.2.0) then took part in the three-card check; its card 0 (firmware 1.4.1) overheats and was left out.

aifoundry2 and aifoundry3 look identical and are not. Same firmware release, same PMIC firmware, same static device configuration over the driver's ioctl: 65 W TDP, 600 MHz boot clock, 32 compute shires, 32 MB of L3 (on 22 September and again in every pass of the three-card check, where aifoundry1's card 1 reports the same). But asked the same question over the management interface, the service processors give different answers.

The governor compares measured SoC power against that TDP level. With the level at zero, the comparison in its power branch (lines 862–887 of the cards' source, §1) can only come out one way:

So on aifoundry3 the step-up request, the only way above 600 MHz, can never fire. In the trace read on 22 September each kernel start logged a power throttle-down request and each return to idle an idle event; the clock read 600 MHz in all 7,745 samples of that session, and in every sample of the three-card check (§9). The service processor's own log, read back out of the card on 22 September, shows the pattern (six consecutive lines, verbatim):

The log, and a second reading that agrees
Power idle state event, current pwr 26220  tdp level 0
Power throttle down event, current pwr 35380  tdp level: 0
Power idle state event, current pwr 26100  tdp level 0
Power throttle down event, current pwr 40200  tdp level: 0
Power idle state event, current pwr 26060  tdp level 0
Power throttle down event, current pwr 48470  tdp level: 0

A second, independent reading agrees. get_power_state() classifies the card as MAX_POWER whenever power exceeds the TDP level and MANAGED_POWER when it is merely above the 30 W safe threshold. aifoundry3 reports max_power while sitting at 23 W and 600 MHz, which is only consistent with a TDP level below 23 W; aifoundry2, drawing more, reports managed_power, and so does aifoundry1's card 1 (every pass of the three-card check read the same). Two different code paths, one cause.

The cards' source predicts that the zero does more than pin the clock: it stops the governor. At the first launch the throttle-down request starts the power loop at the table's first point. That loop exits only when the PMIC average falls below 1.05 × 0 W or the clock reaches 300 MHz; a step down from the first point leaves the frequency unchanged, and an unchanged frequency returns at once (2238–2246, 1788–1791). So the power task spins in the loop, reading the PMIC over I2C, and never serves another request. The device-management pass still logs the alternating throttle-down and idle lines, because it sets the state itself, which is what 22 September shows. The first time the mean then passes 65 °C, the pass sets the thermal state, and only the spinning task could clear it (668–679, 844–845): from then on no governor line of any kind is logged, and the PMIC's safe state, which the same task would serve, cannot act either. This is an inference from the source, consistent with every reading; aifoundry3's longer service-processor pass (§1) would also fit a task spinning on I2C reads, which is not established.

The host cannot see this. The driver's ETSOC1_IOCTL_GET_DEVICE_CONFIGURATION reports a 65 W TDP on all three machines, including aifoundry3. Anything that checks a card's configuration from the host side gets the nameplate number, not the one the governor is using. The card works. It is simply held at 600 MHz for as long as its TDP stays at zero, which on a compute-bound workload that would otherwise run at 800 MHz gives up a quarter of the throughput (800 MHz is a third faster than 600), and nothing reports an error. The zero is not flashed: a boot service on aifoundry3, in place since July with a note that the card is unreliable above 600 MHz, sets the TDP level to 0 and the minion and mesh clocks to 600 and 400 MHz at every boot, through the management commands; a card reset returns the card to its firmware's own DVFS until the service runs again. It is the lab's deliberate setting (the lab's card notes).

How this compares with aifoundry2's own throttling, and what it settles

The contrast is not that aifoundry2 is always faster. Launched warm, it too runs at 600 MHz: the thermal branch holds it at the floor, and every one of the strict protocol's launches at 80 °C ran at 600 MHz (§1). The difference is the remedy. aifoundry2 reaches 700 and 800 MHz when it starts cool (§2). aifoundry3 cannot at any temperature, because the branch that would raise it is unreachable.

This also bears on what §2 could not settle: whether the power branch works at all. It never fired on its own in any aifoundry2 run. On aifoundry3, in the 22 September window, it was the only branch that fired, at every kernel start, on a die well below the thermal threshold, as the comparison says it will; the three-card check's windows hold no governor line to repeat that, as the cards' source predicts once the governor is stuck (above). That the branch lowers a clock that is above the floor is not shown alone on either card; aifoundry2's fastest drop, two steps within 0.1 s at 87.8 W, fits only its no-delay power loop, and its one-step drop at 87.5 W fits that loop or a thermal episode of zero steps (§2).

4. The leakage-suppression transistors

Kanter's mechanism is a tag check that wakes only the part of an array a lookup needs, at a small wake-up latency; the same trick applies to whole cores and execution units.

The design has the ports. The open RTL of the neighbourhood (a group of eight minions) carries the full interface: a per-minion sleep control and its acknowledge (pwr_ctrl_min_nsleepin / nsleepout, one bit per minion), a global pair, and per-minion isolation (pwr_ctrl_min_isolate) with level shifters and a power stub that forces the outputs safe while a domain is down. That is a textbook power-gating structure, sized for the granularity he described.

Why this doesn't cover L2/L3

That RTL is the Erbium configuration (one neighbourhood, no shire cache), so it says nothing about the L2 and L3 arrays; for those, the wake-up probe below is the only evidence.

Nothing drives it. In the open configuration the whole interface is tied off, with a comment saying so:

The tied-off RTL, verbatim, and the firmware search behind it
// Power Ctrl - power control handled outside cpu subsystem and this ifce is not used
.pwr_ctrl_glb_nsleepin ('1),   // '1 = never asleep
.pwr_ctrl_min_nsleepin ('1),
.pwr_ctrl_min_isolate  ('0),

And the service-processor firmware, searched both at 353f20e and in the older governor, contains no power-gating control of any kind: its only PWR_CTRL hits are an eMMC controller's bus voltage, and elsewhere in the tree the name appears only in eMMC and PCIe PHY register headers. Whatever drives those pins on the taped-out part, it is not this firmware, and the chip-level netlist is not in the open release.

How the wake-up probe works

And no card shows any sign of it. If an array were suppressed once idle, the first access afterwards would pay the wake-up. The probe: put one line at a chosen level, let the minion spin on its cycle counter for a swept interval from zero to 27 ms (0, 1.7 µs, 17 µs … 27 ms) without touching that line, then time a single load of it: same line, same address, only the idle time varying, 20 repeats. It ran once on aifoundry2 on 22 September (the chart), and three times on each of the three cards in the three-card check (the table below it). (The probe counts the idle in cycles; the times assume 600 MHz. On 22 September the clock during the probe was not recorded; aifoundry2 was resting at about 73 °C that morning, and in 26 sessions on five days it never ran above 600 MHz at a die reading of 68 °C or more. In the check it was recorded, and read 600 MHz before and after every probe.)

Every repeat of the wake-up probe: each line is one repeat's load latency after the idle, minus the same line's latency with no idle

The same probe on three cards, 26 September, against the probe charted above

So on these three cards, in their firmware (1.3.1 on two, 1.2.0 on aifoundry1's card 1), no leakage suppression is in use. The open design has the ports and ties them off, no firmware line drives them, and no card shows a wake-up. Whether the taped-out chip could gate its arrays is not established (§9). The gating the open RTL does use is clock gating, and aggressively (per lane, per functional unit, with a seven-cycle tail). That is the likely reason a powered core that is not computing costs little dynamic power (Why is the ET-SoC-1 low power?, section 4; in the three-card check an integer spin loop on all 1,024 minions drew ) and still leaks.

5. What that costs

What the idle readings fix is the slope. On aifoundry2, idle power climbs W for every degree of die temperature at 80 °C. The law below, fitted to its idle readings, splits idle power into a fixed part and a leakage part that grows exponentially with temperature. Its total and its slope are well determined; the split is not. Leakage temperature scales (the 36 °C in the exponent) anywhere from °C fit the readings about as well, and put W of the 80 °C idle in leakage and W in the fixed part, with the slope at W/°C throughout. The equation and the chart's shading are the central fit; the chart's share strip carries the range. The law is one fit, made on one day: the three-card check's overnight idle passes, which were to refit it, did not run, so its constants are not re-measured (its short cooling cycles test the law below).

One law, and the checks on it: idle power against die temperature

Cross-checks: the 22 September session, and the unsensed rails

Checks the fit never saw. The idle law above was fitted on aifoundry2 on 21 September to idle readings at °C (the Horace experiment, §8; tabulated in the energy manual, §1). It predicts . . In that one 22 September session, nearly half of the idle, W, is on no rail sensor (energy manual, §1). .

Leakage transfers, but not as a constant.

Every idle session against the law, session by session
Every idle session against the law: measured minus law, one row per card and campaign

Each mark is one idle session from the table below, measured minus the law over its idle samples; the bar under each row is that row's mean ± one standard deviation. The first rows are the sessions of 21–24 September; the last are the three-card check's cooling cycles of 26 September, 15 minutes each from 88–90 °C, whose single figure averages a gap that grows with temperature on aifoundry3 and aifoundry1's card 1 (the law chart's second button shows it degree by degree). Zero is the law fitted on aifoundry2.

aifoundry3's first session bin by bin, and every session and cooling cycle the law was not fitted on, against the aifoundry2 law

Each session's idle samples are the 600 MHz samples outside [launch start − 1 s, launch end + 6 s], binned by whole degree (bins of 20 samples or more); the session's figure is measured minus law over those samples. The 22 September idle has no launches, so all of it counts. A cooling cycle counts only its 900 s of cooling, the check's own window, so its bins are the check's.

Three things plausibly make the leakage share high (above Kanter's 5–30% at idle, whatever the split), and only the third is the chip's own: (1) it runs at 0.52 V rather than the 0.4 V Esperanto designed for; (2) aifoundry2's desktop chassis rests it at 62–74 °C (§8 for one night's swing), and these shares are quoted at 80 °C; server airflow would keep it cooler, and at °C, where aifoundry3 ran in another machine, the same law puts leakage at of a busy card; (3) it carries 128 MB of shire SRAM (Esperanto quotes over 160 MB on die, at Hot Chips 33) with no array power gating in play. Only (2) has data behind it here; (1) and (3) are reasoning, since no run varies the voltage alone or gates the SRAM (the voltage has moved only with the clock, and how much of that step is leakage was not measured: Why is the ET-SoC-1 low power?, Voltage and clock). The law above is aifoundry2's; the energy manual refits it for aifoundry3 and aifoundry1's card 1 from the check's cooling cycles (its §7).

6. What the other cards say about the model

The three-card check of 26 September re-ran eight of these patterns, four runs each, on aifoundry2, aifoundry3 and aifoundry1's card 1. As registered, the same model needs a factor of 0.88 on aifoundry3 and 0.99 on aifoundry1's card 1 (0.99 on aifoundry2 itself). Most of aifoundry3's deficit is the reduction's fixed reference temperature (post-data note C2): at each run's own launch temperature the factors are 0.93–0.95 on aifoundry3, 0.96–1.00 on aifoundry1's card 1 and 0.96–0.99 on aifoundry2, over the two readings of the whole-degree launch temperature. A test at two launch temperatures could not say whether what remains is the card or its temperature (the Horace experiment, §10).

7. What this means for the equation, and for measuring power

The MLPerf cost argument, and the hunting-vs-provisioned-power point

8. What triggers a step down, and does placement delay it

A development night, then a frozen validation.

The owner asked two things after the three-card check: does voltage-frequency scaling act on the average temperature or on one hot shire, and can the same computation run longer before it is throttled in some places on the chip? §1 answers the first from the source. The development night asked aifoundry2, the only card whose governor moves the clock, and wrote down beforehand what each answer would look like. It also set the rules for a validation, which ran on the same card from the evening of 28 September to the afternoon of 29 September; its verdicts close this section.

What the validation answered.

What ran on the night, and how one run works

Every step that fitted a rule fitted the mean.

One launch at 800 MHz, a 10 Hz sample at a time: the clock, the 34-sensor mean the governor compares, and the hottest sensor (development, 28 September)

When the step came in each run that tells the two rules apart, against each reading's first 66 °C (the frozen validation's runs, or the development night's)

Placed on the perimeter, the same work held 800 MHz longer.

Seconds at 800 MHz before the first step, interior against perimeter placement, block by block (the frozen validation, 28–29 September, or the development night, 28 September)

The loop, line by line.

Every time the idle card entered and left the thermal loop within a minute: the interval between the two governor lines, against whole periods of the loop (development, 27–28 September)

The card's rest swings, and the governor follows it.

The night on aifoundry2: the idle mean and hottest sensor at each watch cycle, the governor's crossings of its threshold, and the heating sessions (development, 27–28 September, PDT)

The frozen validation (28–29 September) and its verdicts.

What each registered item tests

28 September 2026, 02:50:53 PDT: aifoundry2's Master Minion hung (restored at 08:32 the same day).

Method and limits of this section

9. Method, and what is not established

All method notes and limits, in full
Reproduce this

To rebuild this report's data and page from the raw files (the wake-up probe itself needs a card):

python3 workloads/memprobe/gen_ops.py wakeup --out W --reps 20 --seed 11 \
    --delays 0,1000,10000,100000,1000000,4000000,8000000,16000000
build/memprobe/host/memprobe_host --program W/wakeup.ops --out-dir W --budget 40

D=docs/reports/data; H=$D/2026-09-21-horace-aifoundry2; A3=$D/2026-09-22-horace-aifoundry3; C=$D/2026-09-22-cards
R2=$D/2026-09-23-reruns-aifoundry2
python3 tools/ettelem/analyze_dvfs.py --cold $H/cold1 $H/cold2 --wakeup $D/2026-09-22-dvfs-aifoundry2/wakeup \
    --idle $D/2026-09-22-dvfs-aifoundry2/idle_20h.jsonl.gz --since $H/long2/runs.jsonl.gz \
    --model $H/model.json --ablation $H/ablation.json --sptrace $C/sptrace-aifoundry3.bin \
    --cool-passes $R2/hotline-pass2 $R2/hotline-pass3 $R2/hotline-pass4 $R2/relay-pass1 $R2/relay-pass2 $R2/relay-pass4 \
    --idle-sessions $H $D/2026-09-2[234]-* --v3 $D/2026-09-25-claims-v3 \
    --out $D/2026-09-22-dvfs-aifoundry2/dvfs.json
python3 tools/ettelem/build_cards_data.py --cards $A3/cards.json --transfer $A3/transfer.json \
    --leak $A3/leakage_crosscard.json --config $C/config.json --driver $C/driver_config.json \
    --sptrace $C/sptrace-aifoundry3.bin --out $C/cards-report.json \
    --merge $D/2026-09-22-dvfs-aifoundry2/dvfs.json
V=$D/2026-09-28-dvfs2-aifoundry2     # §8: the development night; its two reductions first
python3 tools/claims-v3/dv2/reduce_dv2.py --dev --data $V/raw --out $V/reductions/dv2-dev.json
python3 tools/claims-v3/dv2v/reduce_val.py --data $V/raw --dev --out $V/reductions/dev-idle.json
python3 tools/claims-v3/dv2v/reduce_val.py --data $V/validation/raw --out $V/validation/verdicts-dv2val.json   # the validation
python3 tools/ettelem/build_dv2_data.py --data $V --merge $D/2026-09-22-dvfs-aifoundry2/dvfs.json
python3 scripts/build-report.py dvfs-leakage $D/2026-09-22-dvfs-aifoundry2/dvfs.json \
    docs/reports/2026-09-22-dvfs-leakage.html

analyze_dvfs.py carries over the blocks the two merges add, and stops rather than drop a block its options would not rebuild; build-report.py refuses data without the cards and dv2 blocks.

Version history

Versions. 22 September 2026: first published for aifoundry2, then the three-machine comparison. 24 September: the governor's pass is about 133 ms, not 10 ms; it hunts on the thermal threshold, not the power guardband; the open RTL is Erbium, not the chip; seven down-steps are unattributed. 25 September: the rule's frequency check sits inside the thermal test, and the DRAM wake-up counts corrected; then version 3: the leakage shares as ranges, and "every result checked was correct" withdrawn. 26 September (version 4), the three-card check: aifoundry3's zero TDP is set by a boot service, not flashed; the busy leakage share is no longer said to exceed 30%. 27 September: the review's fixes (verdict row 6 cut) and charts. 28 September: §1 rewritten for the governor the cards run (firmware 0.20.0), with §2's steps explained by it; aifoundry3's zero limit stops its governor and aifoundry1's card 1's governor is inactive; no firmware temperature limit at the lowest point; a new §8, the night of 27–28 September; later, the review's cuts; then the card's restore at 08:32, and aifoundry3's query and placement runs pointed to their data. 29 September: §8's validation, started at 20:45 PDT on 28 September, its three heating sessions done and its reduction due after about 16:45 PDT; that evening, its verdicts (TH3, TH4 and TH8 survived, TH7 fell, and the owner's two questions stayed untested), the validation's runs in the charts of the two questions, and "seven complete placement blocks" corrected to four. What each version changed in full: this page's history in the repository.